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ADC1206S040/055/070
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
Rev. 02 -- 12 August 2008 Product data sheet
1. General description
The ADC1206S040/055/070 are a family of BiCMOS 12-bit Analog-to-Digital Converters (ADC) optimized for a wide range of applications such as cellular infrastructures, professional telecommunications, imaging, and digital radio. It converts the analog input signal into 12-bit binary coded digital words at a maximum sampling rate of 70 MHz. All static digital inputs (SH, CE and OTC) are Transistor-Transistor Logic (TTL) and CMOS compatible and all outputs are CMOS compatible. A sine wave clock input signal can also be used.
2. Features
I I I I I I I I I I I I I I I I 12-bit resolution Sampling rate up to 70 MHz -3 dB bandwidth of 245 MHz 5 V power supplies and 3.3 V output power supply Binary or twos complement CMOS outputs In-range CMOS compatible output TTL and CMOS compatible static digital inputs TTL and CMOS compatible digital outputs Differential AC or Positive Emitter-Coupled Logic (PECL) clock input; TTL compatible Power dissipation 550 mW (typical) Low analog input capacitance (typical 2 pF), no buffer amplifier required Integrated sample and hold amplifier Differential analog input External amplitude range control Voltage controlled regulator included -40 C to +85 C ambient temperature
3. Applications
High-speed analog-to-digital conversion for: I Cellular infrastructure I Professional telecommunication I Digital radio I Radar I Medical imaging I Fixed network I Cable modem
NXP Semiconductors
ADC1206S040/055/070
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
I Barcode scanner I Cable Modem Termination System (CMTS)/ Data Over Cable Service Interface Specification (DOCSIS)
4. Quick reference data
Table 1. Quick reference data VCCA = V2 to V44, V3 to V4 and V41 to V40 = 4.75 V to 5.25 V; VCCD = V37 to V38 and V15 to V17 = 4.75 V to 5.25 V; VCCO = V33 to V34 = 3.0 V to 3.6 V; AGND and DGND shorted together; Tamb = -40 C to 85 C; VI(IN)(p-p) - VI(INN)(p-p) = 1.9 V; Vref = VCCA3 - 1.75 V; VI(cm) = VCCA3 - 1.6 V; typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V, Tamb = 25 C and CL = 10 pF; unless otherwise specified. Symbol VCCA VCCD VCCO ICCA ICCD ICCO INL DNL Parameter analog supply voltage digital supply voltage output supply voltage analog supply current digital supply current output supply current integral non-linearity differential non-linearity fclk = 20 MHz fi = 400 kHz fclk = 20 MHz fi = 400 kHz fclk = 20 MHz fi = 400 kHz (no missing code guaranteed) ADC1206S040H ADC1206S055H ADC1206S070H Ptot total power dissipation fclk = 55 MHz fi = 20 MHz Conditions Min 4.75 4.75 3.0 Typ 5.0 5.0 3.3 78 27 3 2.6 0.5 Max 5.25 5.25 3.6 87 30 4 4.5 Unit V V V mA mA mA LSB
+1.1 - 0.95 LSB
fclk(max)
maximum clock frequency
40 55 70 -
550
660
MHz MHz MHz mW
5. Ordering information
Table 2. Ordering information Package Name ADC1206S040H ADC1206S055H ADC1206S070H QFP44 QFP44 QFP44 Description plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm Version Sampling frequency (MHz) Type number
SOT307-2 40 SOT307-2 55 SOT307-2 70
ADC1206S040_055_070_2
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 -- 12 August 2008
2 of 32
NXP Semiconductors
ADC1206S040/055/070
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
6. Block diagram
VCCA1 2 6 to 10,13,14,16 n.c. 12
VCCA3 3
VCCA4 CLKN 41 35
CLK 36
VCCD1 37
VCCD2 15
OTC 18
CE 19
FSREF
Vref REFERENCE
CLOCK DRIVER
ADC1206S040/055/070
Vref
11 21 D11 22 D10 23 D9 AMP 24 D8 25 D7 MSB
INN IN
43 42 ANALOG - TO DIGITAL CONVERTER
LATCHES
CMOS OUTPUTS
26 D6 27 D5 28 D4 29 D3 data outputs
sample and - hold
SH
39
30 D2 31 D1 32 D0 33 LSB
VCCO
CMADC
1 5
CMADC REFERENCE
OVERFLOW/UNDERFLOW LATCH
CMOS OUTPUT
20
IR
DEC 44 4 40 38 17 34
AGND1
AGND3
AGND4
DGND1
DGND2
OGND
014aaa385
Fig 1. Block diagram.
ADC1206S040_055_070_2
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 -- 12 August 2008
3 of 32
NXP Semiconductors
ADC1206S040/055/070
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
7. Pinning information
7.1 Pinning
38 DGND1 44 AGND1 40 AGND4 34 OGND 33 VCCO 32 D0 31 D1 30 D2 29 D3 28 D4 27 D5 26 D6 25 D7 24 D8 23 D9 FSREF 12 n.c. 13 n.c. 14 VCCD2 15 n.c. 16 DGND2 17 OTC 18 CE 19 IR 20 D11 21 D10 22
014aaa383
37 VCCD1
41 VCCA4
CMADC VCCA1 VCCA3 AGND3 DEC n.c. n.c. n.c. n.c.
1 2 3 4 5 6 7 8 9
ADC1206S070H
n.c. 10 Vref 11
Fig 2.
Pin configuration
7.2 Pin description
Table 3. Symbol CMADC VCCA1 VCCA3 AGND3 DEC n.c. n.c. n.c. n.c. n.c. Vref FSREF n.c. n.c. VCCD2 n.c. Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Description regulator output common mode ADC input analog supply voltage 1 (5 V) analog supply voltage 3 (5 V) analog ground 3 decoupling node not connected not connected not connected not connected not connected reference voltage input full-scale reference output not connected not connected digital supply voltage 2 (5 V) not connected
ADC1206S040_055_070_2
35 CLKN
36 CLK
43 INN
39 SH
42 IN
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 -- 12 August 2008
4 of 32
NXP Semiconductors
ADC1206S040/055/070
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
Pin description ...continued Pin 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Description digital ground 2 control input twos complement output; active HIGH chip enable input (CMOS level; active LOW) in-range output data output; bit 11 (Most Significant Bit (MSB)) data output; bit 10 data output; bit 9 data output; bit 8 data output; bit 7 data output; bit 6 data output; bit 5 data output; bit 4 data output; bit 3 data output; bit 2 data output; bit 1 data output; bit 0 (Least Significant Bit (LSB)) output supply voltage (3.3 V) output ground complementary clock input clock input digital supply voltage 1 (5 V) digital ground 1 sample-and-hold enable input (CMOS level; active HIGH) analog ground 4 analog supply voltage 4 (5 V) analog input voltage complementary analog input voltage analog ground 1
Table 3. Symbol DGND2 OTC CE IR D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 VCCO OGND CLKN CLK VCCD1 DGND1 SH AGND4 VCCA4 IN INN AGND1
8. Limiting values
Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VCCA VCCD VCCO VCC Parameter analog supply voltage digital supply voltage output supply voltage supply voltage difference VCCA - VCCD VCCD - VCCO VCCA - VCCO Conditions
[1] [1] [1]
Min -0.3 -0.3 -0.3 -1.0 -1.0 -1.0
Max +7.0 +7.0 +7.0 +1.0 +4.0 +4.0
Unit V V V V V V
ADC1206S040_055_070_2
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 -- 12 August 2008
5 of 32
NXP Semiconductors
ADC1206S040/055/070
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
Table 4. Limiting values ...continued In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Vi(IN) Vi(INN) Vi(clk)(p-p) IO Tstg Tamb Tj
[1]
Parameter input voltage on pin IN input voltage on pin INN peak-to-peak clock input voltage output current storage temperature ambient temperature junction temperature
Conditions referenced to AGND differential clock drive at pins 35 and 36
Min 0.3 0.3 -55 -40 -
Max VCCA VCCA VCCD 10 +150 +85 150
Unit V V V mA C C C
The supply voltages VCCA, VCCD and VCCO may have any value between -0.3 V and +7.0 V provided that the supply voltage differences VCC are respected.
9. Thermal characteristics
Table 5. Symbol Rth(j-a) Thermal characteristics Parameter thermal resistance from junction to ambient Conditions in free air Typ 75 Unit K/W
10. Characteristics
Table 6. Characteristics VCCA = V2 to V44, V3 to V4 and V41 to V40 = 4.75 V to 5.25 V; VCCD = V37 to V38 and V15 to V17 = 4.75 V to 5.25 V; VCCO = V33 to V34 = 3.0 V to 3.6 V; AGND and DGND shorted together; Tamb = -40 C to 85 C; VI(IN)(p-p) - VI(INN)(p-p) = 1.9 V; Vref = VCCA3 - 1.75 V; VI(cm) = VCCA3 - 1.6 V; typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V, Tamb = 25 C and CL = 10 pF; unless otherwise specified. Symbol Supplies VCCA VCCD VCCO ICCA ICCD ICCO analog supply voltage digital supply voltage output supply voltage analog supply current digital supply current output supply current fclk = 20 MHz; fi = 400 kHz fclk = 55 MHz; fi = 20 MHz Ptot total power dissipation fclk = 55 MHz fi = 20 MHz I I I I 4.75 4.75 3.0 5.0 5.0 3.3 78 27 3 6.2 9.5 550 5.25 5.25 3.6 87 30 4 9 12 660 V V V mA mA mA mA mA mW Parameter Conditions Test Min
[1]
Typ
Max
Unit
fclk = 40 MHz; fi = 4.43 MHz C
ADC1206S040_055_070_2
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 -- 12 August 2008
6 of 32
NXP Semiconductors
ADC1206S040/055/070
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
Table 6. Characteristics ...continued VCCA = V2 to V44, V3 to V4 and V41 to V40 = 4.75 V to 5.25 V; VCCD = V37 to V38 and V15 to V17 = 4.75 V to 5.25 V; VCCO = V33 to V34 = 3.0 V to 3.6 V; AGND and DGND shorted together; Tamb = -40 C to 85 C; VI(IN)(p-p) - VI(INN)(p-p) = 1.9 V; Vref = VCCA3 - 1.75 V; VI(cm) = VCCA3 - 1.6 V; typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V, Tamb = 25 C and CL = 10 pF; unless otherwise specified. Symbol Inputs CLK and CLKN referenced to DGND[2] VIL VIH IIL IIH Vi(dif)(p-p) LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input current peak-to-peak differential input voltage input resistance input capacitance LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input current LOW-level input current HIGH-level input current input resistance input capacitance VIL = 0.8 V VIH = 2.0 V PECL mode; VCCD = 5 V TTL mode PECL mode; VCCD = 5 V TTL mode VCLK or VCLKN = 3.19 V VCLK or VCLKN = 3.83 V AC driving mode; DC voltage level = 2.5 V fclk = 55 MHz fclk = 55 MHz I C I C C C C 3.19 0 3.83 2.0 -10 1 1.5 3.52 0.8 4.12 VCCD 10 2.0 V V V V A A V Parameter Conditions Test Min
[1]
Typ
Max
Unit
Ri Ci
D D
2 -
-
2
k pF
OTC, SH and CE (referenced to DGND); see Table 8 and 9 VIL VIH IIL IIH I I I I 0 2.0 -20 0.8 VCCD 20 V V A A
IN and INN (referenced to AGND); see Table 7, Vref = VCCA3 - 1.75 V IIL IIH Ri Ci VI(cm) SH = HIGH SH = HIGH fi = 20 MHz fi = 20 MHz C C D D C VCCA3 - 1.7 10 10 14 450 VCCA3 - 1.6 A A M pF
common-mode VI(IN) = VI(INN) input voltage output code 2047 common-mode output voltage load current
VCCA3 - 1.2 V
Voltage controlled regulator output CMADC VO(cm) Iload I I VCCA3 - 1.6 1 2 V mA
ADC1206S040_055_070_2
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 -- 12 August 2008
7 of 32
NXP Semiconductors
ADC1206S040/055/070
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
Table 6. Characteristics ...continued VCCA = V2 to V44, V3 to V4 and V41 to V40 = 4.75 V to 5.25 V; VCCD = V37 to V38 and V15 to V17 = 4.75 V to 5.25 V; VCCO = V33 to V34 = 3.0 V to 3.6 V; AGND and DGND shorted together; Tamb = -40 C to 85 C; VI(IN)(p-p) - VI(INN)(p-p) = 1.9 V; Vref = VCCA3 - 1.75 V; VI(cm) = VCCA3 - 1.6 V; typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V, Tamb = 25 C and CL = 10 pF; unless otherwise specified. Symbol Parameter Conditions Test Min
[1]
Typ
Max
Unit
Voltage input Vref[3] Vref Iref Vi(dif)(p-p) reference voltage reference current peak-to-peak differential input voltage reference output voltage LOW-level output voltage HIGH-level output voltage output current VI(IN)(p-p) - VI(INN)(p-p); Vref = VCCA3 - 1.75 V; VI(cm) = VCCA3 - 1.6 V full-scale fixed voltage; fi = 20 MHz; fclk = 55 MHz C C C VCCA3 - 1.75 0.3 1.9 10 V A V
Voltage controlled regulator output FSREF VO(ref) VI(IN)(p-p) - VI(INN)(p-p) = 1.9 V I VCCA3 - 1.75 V
Digital outputs D11 to D0 and IR (referenced to OGND) VOL VOH Io IOL = 2 mA IOH = - 0.4 mA 3-state output level between 0.5 V and VCCO SH = HIGH I I I 0 0.5 VCCO +20 V V A
VCCCO - 0.5 -20 -
Switching characteristics; Clock frequency fclk; see Figure 3 fclk(min) fclk(max) minimum clock frequency C C I C C C 40 55 70 6.8 6.8 7 MHz MHz MHz MHz ns ns
maximum clock ADC1206S040H frequency ADC1206S055H ADC1206S070H HIGH clock pulse width LOW clock pulse width fi = 20 MHz fi = 20 MHz
tw(clk)H tw(clk)L
Analog signal processing; 50 % clock duty factor; VI(IN)(p-p) - VI(INN)(p-p) = 1.9 V; Vref = VCCA3 - 1.75 V; see Table 7 Linearity INL DNL integral non-linearity differential non-linearity offset error fclk = 20 MHz; fi = 400 kHz fclk = 20 MHz; fi = 400 kHz (no missing code guaranteed) VCCA = VCCD = 5 V; VCCO = 3.3 V; Tamb = 25 C; output code = 2047 spread from device to device; VCCA = VCCD = 5 V; VCCO = 3.3 V; Tamb = 25 C I I 2.6 0.5 4.5 LSB
+1.1 - 0.95 LSB
Eoffset
C
-25
+5
+25
mV
EG
gain error
C
-7
-
+7
%FS
ADC1206S040_055_070_2
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 -- 12 August 2008
8 of 32
NXP Semiconductors
ADC1206S040/055/070
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
Table 6. Characteristics ...continued VCCA = V2 to V44, V3 to V4 and V41 to V40 = 4.75 V to 5.25 V; VCCD = V37 to V38 and V15 to V17 = 4.75 V to 5.25 V; VCCO = V33 to V34 = 3.0 V to 3.6 V; AGND and DGND shorted together; Tamb = -40 C to 85 C; VI(IN)(p-p) - VI(INN)(p-p) = 1.9 V; Vref = VCCA3 - 1.75 V; VI(cm) = VCCA3 - 1.6 V; typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V, Tamb = 25 C and CL = 10 pF; unless otherwise specified. Symbol Parameter Conditions Test Min
[1]
Typ
Max
Unit
Bandwidth (fclk = 55 MHz)[4] B Harmonics 2H second harmonic level ADC1206S040H; (fclk = 40 MHz) fi = 4.43 MHz fi = 10 MHz fi = 15 MHz fi = 20 MHz fi = 4.43 MHz fi = 10 MHz fi = 15 MHz fi = 20 MHz fi = 4.43 MHz fi = 10 MHz fi = 15 MHz 3H third harmonic level fi = 4.43 MHz fi = 10 MHz fi = 15 MHz fi = 20 MHz fi = 4.43 MHz fi = 10 MHz fi = 15 MHz fi = 20 MHz fi = 4.43 MHz fi = 10 MHz fi = 15 MHz C C C C C C C I C C C C C C C C C C I C C C -78 -77 -74 -71 -77 -77 -76 -73 -76 -74 -70 -74 -74 -74 -73 -74 -74 -74 -72 -74 -74 -73 dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS bandwidth -3 dB; full-scale input C 220 245 MHz
ADC1206S055H; (fclk = 55 MHz)
ADC1206S070H; (fclk = 70 MHz)
ADC1206S040H; (fclk = 40 MHz)
ADC1206S055H; (fclk = 55 MHz)
ADC1206S070H; (fclk = 70 MHz)
ADC1206S040_055_070_2
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 -- 12 August 2008
9 of 32
NXP Semiconductors
ADC1206S040/055/070
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
Table 6. Characteristics ...continued VCCA = V2 to V44, V3 to V4 and V41 to V40 = 4.75 V to 5.25 V; VCCD = V37 to V38 and V15 to V17 = 4.75 V to 5.25 V; VCCO = V33 to V34 = 3.0 V to 3.6 V; AGND and DGND shorted together; Tamb = -40 C to 85 C; VI(IN)(p-p) - VI(INN)(p-p) = 1.9 V; Vref = VCCA3 - 1.75 V; VI(cm) = VCCA3 - 1.6 V; typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V, Tamb = 25 C and CL = 10 pF; unless otherwise specified. Symbol Parameter Conditions Test Min
[1]
Typ
Max
Unit
Total harmonic distortion[5] THD total harmonic distortion ADC1206S040H; (fclk = 40 MHz) fi = 4.43 MHz fi = 10 MHz fi = 15 MHz fi = 20 MHz fi = 4.43 MHz fi = 10 MHz fi = 15 MHz fi = 20 MHz fi = 4.43 MHz fi = 10 MHz fi = 15 MHz Thermal noise (fclk = 55 MHz) Nth(RMS) RMS thermal noise signal-to-noise ratio shorted input; SH = HIGH; fclk = 55 MHz C 0.45 LSB C C C C C C C I C C C -68 -68 -68 -68 -68 -68 -68 -68 -68 -67 -67 dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS
ADC1206S055H; (fclk = 55 MHz)
ADC1206S070H; (fclk = 70 MHz)
Signal-to-noise ratio[6] S/N ADC1206S040H; (fclk = 40 MHz) fi = 4.43 MHz fi = 10 MHz fi = 15 MHz fi = 20 MHz fi = 4.43 MHz fi = 10 MHz fi = 15 MHz fi = 20 MHz fi = 4.43 MHz fi = 10 MHz fi = 15 MHz C C C C C C C I C C C 64 64 64 64 64 64 64 64 64 64 63 dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS
ADC1206S055H; (fclk = 55 MHz)
ADC1206S070H; (fclk = 70 MHz)
ADC1206S040_055_070_2
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 -- 12 August 2008
10 of 32
NXP Semiconductors
ADC1206S040/055/070
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
Table 6. Characteristics ...continued VCCA = V2 to V44, V3 to V4 and V41 to V40 = 4.75 V to 5.25 V; VCCD = V37 to V38 and V15 to V17 = 4.75 V to 5.25 V; VCCO = V33 to V34 = 3.0 V to 3.6 V; AGND and DGND shorted together; Tamb = -40 C to 85 C; VI(IN)(p-p) - VI(INN)(p-p) = 1.9 V; Vref = VCCA3 - 1.75 V; VI(cm) = VCCA3 - 1.6 V; typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V, Tamb = 25 C and CL = 10 pF; unless otherwise specified. Symbol Parameter Conditions Test Min
[1]
Typ
Max
Unit
Spurious free dynamic range; see Figure 7, 13 and 14 SFDR spurious free dynamic range ADC1206S040H; (fclk = 40 MHz) fi = 4.43 MHz fi = 10 MHz fi = 15 MHz fi = 20 MHz fi = 4.43 MHz fi = 10 MHz fi = 15 MHz fi = 20 MHz fi = 4.43 MHz fi = 10 MHz fi = 15 MHz Effective number of bits[7] ENOB effective number of bits ADC1206S040H; (fclk = 40 MHz) fi = 4.43 MHz fi = 10 MHz fi = 15 MHz fi = 20 MHz fi = 4.43 MHz fi = 10 MHz fi = 15 MHz fi = 20 MHz fi = 4.43 MHz fi = 10 MHz fi = 15 MHz Two-tone Intermodulation; (fclk = 55 MHz; fi = 20 IM IMD3 intermodulation suppression third-order intermodulation distortion MHz)[8] C C -68 -70 dB dB C C C C C C C I C C C 10.1 10.1 10.1 10 10.1 10.1 10 10 10 10 10 bits bits bits bits bits bits bits bits bits bits bits C C C C C C C I C C C 72 71 71 69 72 71 71 69 70 69 69 dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS
ADC1206S055H; (fclk = 55 MHz)
ADC1206S070H; (fclk = 70 MHz)
ADC1206S055H; (fclk = 55 MHz)
ADC1206S070H; (fclk = 70 MHz)
ADC1206S040_055_070_2
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 -- 12 August 2008
11 of 32
NXP Semiconductors
ADC1206S040/055/070
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
Table 6. Characteristics ...continued VCCA = V2 to V44, V3 to V4 and V41 to V40 = 4.75 V to 5.25 V; VCCD = V37 to V38 and V15 to V17 = 4.75 V to 5.25 V; VCCO = V33 to V34 = 3.0 V to 3.6 V; AGND and DGND shorted together; Tamb = -40 C to 85 C; VI(IN)(p-p) - VI(INN)(p-p) = 1.9 V; Vref = VCCA3 - 1.75 V; VI(cm) = VCCA3 - 1.6 V; typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V, Tamb = 25 C and CL = 10 pF; unless otherwise specified. Symbol Parameter Conditions Test Min
[1]
Typ
Max
Unit
Bit error rate (fclk = 55 MHz) BER bit error rate fi = 20 MHz; VI = 16 LSB at C code 2047 C C C 10-14 times/sample
Timing (CL = 10 pF)[9] td(s) th(o) td(o) sampling delay time output hold time output delay time float to active HIGH delay time float to active LOW delay time active HIGH to float delay time active LOW to float delay time 4 0.25 6.4 9.0 1 13 ns ns ns
3-state output delay times; see Figure 4 tdZH C 5.1 9.0 ns
tdZL
C
-
7.0
11
ns
tdHZ tdLZ
C C
-
9.7 9.5
14 13
ns ns
[1] [2]
D = guaranteed by design; C = guaranteed by characterization; I = 100 % industrially tested. The circuit has two clock inputs: CLK and CLKN. There are 5 modes of operation: a) PECL mode 1: (DC level vary 1:1 with VCCD) CLK and CLKN inputs are at differential PECL levels. b) PECL mode 2: (DC level vary 1:1 with VCCD) CLK input is at PECL level and sampling is taken on the falling edge of the clock input signal. A DC level of 3.65 V has to be applied on CLKN decoupled to GND via a 100 nF capacitor. c) PECL mode 3: (DC level vary 1:1 with VCCD) CLKN input is at PECL level and sampling is taken on the rising edge of the clock input signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a 100 nF capacitor. d) Differential AC driving mode 4: When driving the CLK input directly and with any AC signal of minimum 1 V (p - p) and with a DC level of 2.5 V, the sampling takes place at the falling edge of the clock signal. When driving the CLKN input with the same signal, sampling takes place at the rising edge of the clock signal. It is recommended to decouple the CLKN or CLK input to DGND via a 100 nF capacitor. e) TTL mode 1: CLK input is at TTL level and sampling is taken on the falling edge of the clock input signal. In that case the CLKN pin has to be connected to the ground. The ADC input range can be adjusted with an external reference connected to Vref pin. This voltage has to be referenced to VCCA; see Figure 12. The -3 dB analog bandwidth is determined by the 3 dB reduction in the reconstructed output, the input being a full-scale sine wave. Total Harmonic Distortion (THD) is obtained with the addition of the first five harmonics: 2 2 2 2 2 ( 2H ) + ( 3H ) + ( 4H ) + ( 5H ) + ( 6H ) THD = 20 log ----------------------------------------------------------------------------------------------------------------------------------------------2 ( 1H ) where 1H is the fundamental harmonic referenced at 0 dB for a full-scale sine wave input; see Figure 6.
[3] [4] [5]
[6]
Signal-to-noise ratio (S/N) takes into account all harmonics above five and noise up to Nyquist frequency; see Figure 8.
ADC1206S040_055_070_2
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 -- 12 August 2008
12 of 32
NXP Semiconductors
ADC1206S040/055/070
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
[7]
Effective number of bits are obtained via a fast Fourier transform (FFT). The calculation takes into account all harmonics and noise up to half of the clock frequency (Nyquist frequency). Conversion to Single-to-noise-and-distortion-ratio (SINAD) is given by SINAD = ENOB x 6.02 + 1.76 dB; see Figure 5. Intermodulation measured relative to either tone with analog input frequencies of 20 and 20.1 MHz. The two input signals have the same amplitude and the total amplitude of both signals provides full-scale to the converter (-6 dB below full-scale for each input signal). IMD3 is the ratio of the RMS value of either input tone to the RMS value of the worst case third order intermodulation product. Output data acquisition: the output data is available after the maximum delay of td(o); see Figure 3.
[8]
[9]
11. Additional information relating to Table 6
Table 7. Code Underflow 0 1 2047 4094 4095 Overflow Table 8. OTC 0 1 X[1]
[1] X = don't care.
Output coding with differential inputs (typical values to AGND); VI(IN)(p-p) - VI(INN)(p-p) = 1.9 V, Vref = VCCA3 - 1.75 V VI(IN)(p-p) VI(INN)(p-p) IR (V) < 3.125 3.125 3.6 4.075 > 4.075 < 4.075 4.075 3.6 3.125 < 3.125 0 1 1 1 1 0 Binary outputs D11 to D0 0000 0000 0000 0000 0000 0000 0000 0000 0001 01 1111 1111 11 1111 1111 1110 1111 1111 1111 1111 1111 1111 Twos complement outputs D11 to D0 10 0000 0000 00 10 0000 0000 00 10 0000 0000 01 11 1111 1111 11 0111 1111 1110 0111 1111 1111 0111 1111 1111
Mode selection CE 0 0 1 D0 to D11 and IR binary; active two's complement; active high-impedance
Table 9. SH 1 0
Sample-and-hold selection Sample-and-hold active inactive; tracking mode
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ADC1206S040/055/070
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
sample N
sample N + 1 tw(clk)L
sample N + 2
tw(clk)H HIGH CLK 50 % LOW sample N sample N + 1 sample N + 2
IN td(s) th(o) HIGH DATA D0 TO D11 DATA N-2 DATA N-1 td(o) DATA N DATA N+1 50 % LOW
014aaa396
Fig 3.
Timing diagram
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Product data sheet
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ADC1206S040/055/070
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
VCCD CE 0V tdHZ HIGH 90 % output data tdLZ HIGH output data LOW 10 % tdZL 50 % LOW tdZH 50 %
50 %
TEST VCCO tdLZ tdZL tdHZ tdZH
S1 VCCO VCCO OGND OGND
ADC1206S 070
3.3 k
S1
15 pF
CE
014aaa397
frequency on pin CE = 100 kHz
Fig 4.
Timing diagram and test conditions of 3-state output delay time
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Product data sheet
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ADC1206S040/055/070
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
10.6 ENOB (bits) 10.2
(1) (2)
014aaa371
-56 THD (dBFS) -60
014aaa372
(3)
9.8
-64
(3)
9.4
-68
(2) (1)
9 1 10 fi (MHz) 100
-72 1 10 fi (MHz) 100
(1) 40 MHz (2) 55 MHz (3) 70 MHz
(1) 40 MHz (2) 55 MHz (3) 70 MHz
Fig 5. Effective Number Of Bits (ENOB) as a function of input frequency (sample device).
Fig 6. Total Harmonic Distortion (THD) as a function of input frequency (sample device).
76 SFDR (dBFS) 72
(1) (2) (3)
014aaa373
66 SNR (dBFS) 65
014aaa374
68
64
(3)
64
63
(1) (2)
60 1 10 fi (MHz) 100
62 1 10 fi (MHz) 100
(1) 40 MHz (2) 55 MHz (3) 70 MHz
(1) 40 MHz (2) 55 MHz (3) 70 MHz
Fig 7. Spurious Free Dynamic Range (SFDR) as a function of input frequency (sample device).
Fig 8. Signal-to-Noise ratio (S/N) as a function of input frequency (sample device).
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Product data sheet
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ADC1206S040/055/070
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
0 power spectrum (dB) -40
014aaa375
-80
-120
-160 0 5 10 15 20 25 30 measured output range (MHz)
Fig 9.
Single-tone; fi = 20 MHz; fclk = 55 MHz.
0 power spectrum (dB) -40
014aaa376
-80
-120
-160 0 5 10 15 20 25 30 measured output range (MHz)
Fig 10. Two-tone; fi 1 = 20 MHz; fi 2 = 20.1 MHz; fclk = 55 MHz.
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Product data sheet
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ADC1206S040/055/070
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
2 output range (INL) 1
014aaa377
0
-1
-2 0 1024 2048 3072 output code 4096
Fig 11. Integral Non-Linearity (INL)
0.6 DNL (LSB) 0.2
014aaa378
-0.2
-0.6 0 1024 2048 3072 output code 4096
Fig 12. Differential Non-Linearity (DNL)
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Product data sheet
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ADC1206S040/055/070
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
80 SFDR (dBFS) 60
014aaa379
(1)
40
(3) (2)
20 -60
-40
-20 Input amplitude (dBFS)
0
(1) fi = 4.43 MHz (2) fi = 20 MHz (3) SFDR = 80 dB
Fig 13. SFDR as a function of input amplitude; VI(IN)(p-p) - VI(INN)(p-p) = 1.9 V; fclk = 40 MHz
80 SFDR (dBFS) 60
014aaa380
(2)
40
(3)
(1)
20 -60
-40
-20 Input amplitude (dBFS)
0
(1) fi = 4.43 MHz (2) fi = 20 MHz (3) SFDR = 80 dB
Fig 14. SFDR as a function of input amplitude; VI(IN)(p-p) - VI(INN)(p-p) = 1.9 V; fclk = 55 MHz
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Product data sheet
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ADC1206S040/055/070
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
72 (dB)
11 2.6
(3)
014aaa382
bits
(Vi - Vi)(p - p) (V) 2.2
68
(2)
10
1.8 64
(1)
9 1.4
60 1.3
1.5
1.7
1.9
8 2.1 2.3 Vref (V)
014aaa381
1 1.3
1.5
1.7
1.9
2.1 2.3 VCCA - Vref (V)
(1) S/N (2) ENOB (3) SFDR
Fig 15. ENOB, SFDR and S/R as a function of Vref; fclk = 55 MHz; fi = 4.43 MHz
Fig 16. ADC full-scale; VI(IN)(p-p) - VI(INN)(p-p) as a function of VCCA - Vref
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Product data sheet
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ADC1206S040/055/070
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
12. Application information
5V
100 nF 220 nF 1:1 100 100
SH mode
5V
100 nF
IN
CLK INN 5V
10 nf
1 5V
100 nF 100 nF
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
100 nF
2 3 4 5 n.c. n.c. n.c. n.c. n.c. 6 7 6 9 10 11
D0 (LSB) D1 D2 D3 D4 D5 D6 D7 D8 D9
ADC1206S070
28 27 26 25 24
Vref
23 12 13 14 15 16 17 18 19 20 21 22 n.c. n.c. IR D10 D11 (MSB)
n.c. 5V
100 nF
chip select input output format select
014aaa386
The analog, digital and output supplies should be separated and decoupled.
Fig 17. Application diagram
TTL input
D PECL MC 100 ELT20
CLKN
ADC1206S 070
CLK CLKN
270
270
TTL input
014aaa387
ADC1206S 070
CLK
014aaa388
Fig 18. Application diagram for differential clock input PECL compatible using a TTL to PECL translator
Fig 19. Application diagram for TTL single-ended clock
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Product data sheet
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ADC1206S040/055/070
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
12.1 Demonstration board
B11
1 VCC
C6 330 nF
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24 B8
J2 CLK2
R4 50
2
C15 10 nF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
VCCO
FL3
VCCO
B5
33
R3 100 C13 100 nF
32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 IC2 D10 D11 IR CE OTC DGND2 n.c. VCCD2 n.c. n.c. FSREF
FL1 C12 100 nF C18 10 nF C5 330 nF FL2 S3 S4
OGND CLKN CLK VCCD1
34 35 36 37 38 39 40 41 42 43 44 1 CMADC 2 VCCA1 3 VCCA3 4 AGDN3 5 DEC 6 n.c. 7 n.c. 8 n.c. 9 n.c. 10 n.c. 11
J3 CLK1
CLK1
C19 10 nF
VCCD
S5 C17 10 nF
DGND1 SH AGND4 VCCA4 IN
VCCA
ADC1206S070
17 16 15 14 13 12 Vref
VCC
C9
J1 220 nF IN
TR1 CMADC
INN AGND1
R9 100
R1 100
MCLT1_6T_KK81
C8 330 nF S1
S2 C16 10 nF C10 100 nF C11 100 nF B7
VCCA
P1 5 k C14 100 nF FL4
VCC
C7 330 nF
VCCA
P2 1 k R6 2.4 K
R7 1.2 k
VCCA
12 V GND
J4 1 J4 2
BYD17G D3
ICI 1 IN
C1 22 F (20 V)
VCC
TM3
VCC
OUT 3
C2 4.7 F (16 V) R2 62
MC78MO5CDT
GND
PMBT 2222A
T1
VCCO
R8 750 D1 LGT679 C3 1 F D2 BZV55C3V6 R5 4.7 k C4 1 F
TP2
VCCO
014aaa370
C8 = close to TR1 pin.
Fig 20. Demonstration board schematic.
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Product data sheet
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ADC1206S040/055/070
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
R1 J1 C9 TR1 B4 1
TM2 J3 1
S5 S1 P1 1 C14 112 C12 IC2 23 1 B5 S2 R7 TM1 S3 S4 FL2 J2 C5 R3 34
R9 C7 FL4 C10 B7 C11 R6 P2
IC1
TM3 R8 R2 T1 R5
C1 C2 D3 J4 1 2 D1 C3 D2
B8
TP2 C4
R4 B11 1
014aaa391
Fig 21. Component placement (top side).
C6
FL3 C8
C19 C15
C13 C16 C17
FL1
C18
014aaa392
Fig 22. Component placement (underside).
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Product data sheet
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NXP Semiconductors
ADC1206S040/055/070
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
014aaa393
Fig 23. PCB layout (top layer).
014aaa394
Fig 24. PCB layout (ground layer).
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Product data sheet
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ADC1206S040/055/070
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
014aaa395
Fig 25. PCB layout (power plane).
12.2 Alternative parts
The following alternative parts are also available:
Table 10. Alternative parts Description Single 10 bits ADC Single 10 bits ADC
[1] [1]
Type number ADC1006S055 ADC1006S070
[1]
Sampling frequency 55 MHz 70 MHz
Pin to pin compatible
12.3 Recommended companion chip
The recommended companion chip is the TDA9901 wide band differential digital controlled variable gain amplifier.
13. Support information
13.1 Non-linearities
13.1.1 Integral Non-Linearity (INL).
It is defined as the deviation of the transfer function from a best fit straight line (linear regression computation). The INL of the code i is obtained from the equation: V in ( i ) - V in ( ideal ) INL ( i ) = ----------------------------------------------S where i = 0 ( 2 - 1 ) and
n
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Product data sheet
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ADC1206S040/055/070
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
S = slope of the ideal straight line = code width; i = code value.
13.1.2 Differential Non-Linearity (DNL).
V in ( i + 1 ) - V in ( i ) It is the deviation in code width from the value of 1 LSB. DNL ( i ) = -------------------------------------------- - 1 S where i = 0 ( 2 - 2 )
n
13.2 Dynamic parameters (single tone)
Figure 26 shows the spectrum of a full-scale input sine wave with frequency ft, conforming to coherent sampling (ft/fs = M/N, where M is the number of cycles and N is number of samples, M and N being relatively prime), and digitized by the ADC under test.
magnitude a1
SFDR
s
a2
a3
ak
measured output range
fs/2
014aaa389
Fig 26. Spectrum of full-scale input sine wave with frequency ft.
Remark: in the following equations, Pnoise is the power of the terms which include the effects of random noise, non-linearities, sampling time errors, and "quantization noise".
13.2.1 Signal-to-noise and distortion (SINAD)
The ratio of the output signal power to the noise-plus-distortion power for a given sample rate and input frequency, excluding the DC component: P signal SINAD [ db ] = 10 log ----------------------------------------P noise + distortion
13.2.2 Effective Number Of Bits (ENOB)
It is derived from SINAD and gives the theoretical resolution an ideal ADC would require to obtain the same SINAD measured on the real ADC. A good approximation gives: ENOB = ( SINAD [ dB ] - ( 1 76 ) ) ( 6 02 )
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ADC1206S040/055/070
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
13.2.3 Total Harmonic Distortion (THD)
The ratio of the power of the harmonics to the power of the fundamental. For k-1 P harmonics harmonics the THD is: THD [ dB ] = 10 log -------------------------P signal where P harmonics = 2 + 3 + P signal =
2 1 2 2 2 k
The value of k is usually 6 (i.e. calculation of THD is done on the first 5 harmonics).
13.2.4 Signal-to-Noise ratio (S/N)
The ratio of the output signal power to the noise power, excluding the harmonics and the P signal DC component. S/N [ dB ] = 10 log ---------------P noise
13.2.5 Spurious Free Dynamic Range (SFDR)
The number SFDR specifies available signal range as the spectral distance between the amplitude of the fundamental and the amplitude of the largest spurious (harmonic and 1 non-harmonic, excluding DC component). SFDR [ dB ] = 20 log ----------------max ( s )
13.3 Intermodulation distortion
13.3.1 Spectral analysis (dual-tone)
014aaa384
0 (dB) -40 IMD3
-80
-120
-160 0 5 10 15 20 25 30 measured output range (HHz)
Fig 27. Spectral analysis (dual-tone)
From a dual-tone input sinusoid (ft 1 and ft 2, these frequencies being chosen according to the coherence criterion), the intermodulation distortion products IMD2 and IMD3 (respectively, 2nd and 3rd order components) are defined, as follows.
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ADC1206S040/055/070
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
13.3.2 IMD2 (IMD3)
The ratio of the RMS value of either tone to the RMS value of the worst second (third) order intermodulation product. The total intermodulation distortion IMD is given by P intermod IMD [ dB ] = 10 log ----------------------P signal where, P intermod = +
2 (f im t1 2 (f im t1
- f t2 ) -
2 ( 2 f t1 im
2 (f im t1
+ f t2 ) +
2 ( 2 f t1 im
2 (f im t1
- 2 f t2 )
+ 2 f t2 ) +
- f t2 ) +
+ f t2 )
P signal = 2 ( f t1 ) + 2 ( f t2 ) and
2 (f ) im t
is the power in the intermodulation component at frequency ft.
13.4 Noise Power Ratio (NPR)
When using a notch-filtered broadband white-noise generator as the input to the ADC under test, the Noise Power Ratio is defined as the ratio of the average out-of-notch to the in-notch power spectral density magnitudes for the FFT spectrum of the ADC output sample set.
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Product data sheet
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ADC1206S040/055/070
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
14. Package outline
QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm SOT307-2
c
y X
A 33 34 23 22 ZE
e E HE wM bp pin 1 index 44 1 bp D HD wM 11 ZD B vM B vM A 12 detail X A A2 (A 3) Lp L
A1
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.1 A1 0.25 0.05 A2 1.85 1.65 A3 0.25 bp 0.4 0.2 c 0.25 0.14 D (1) 10.1 9.9 E (1) 10.1 9.9 e 0.8 HD 12.9 12.3 HE 12.9 12.3 L 1.3 Lp 0.95 0.55 v 0.15 w 0.15 y 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 10 o 0
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT307-2 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION
ISSUE DATE 97-08-01 03-02-25
Fig 28. SOT307-2 (QFP44)
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Product data sheet
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ADC1206S040/055/070
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
15. Revision history
Table 11. Revision history Release date 20080812 Data sheet status Product data sheet Change notice Supersedes ADC1206S040_055_070_1 Document ID ADC1206S040_055_070_2 Modifications:
* * *
Corrections made to DNL value in Table 1. Corrections made to several entries in Table 6. Corrections made to note in Figure 4. Product data sheet -
ADC1206S040_055_070_1
20080612
ADC1206S040_055_070_2
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Product data sheet
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ADC1206S040/055/070
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
16. Legal information
16.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Quick reference data -- The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding.
16.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
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Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
18. Contents
1 2 3 4 5 6 7 7.1 7.2 8 9 10 11 12 12.1 12.2 12.3 13 13.1 13.1.1 13.1.2 13.2 13.2.1 13.2.2 13.2.3 13.2.4 13.2.5 13.3 13.3.1 13.3.2 13.4 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Thermal characteristics. . . . . . . . . . . . . . . . . . . 6 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Additional information relating to Table 6 . . . 13 Application information. . . . . . . . . . . . . . . . . . 21 Demonstration board . . . . . . . . . . . . . . . . . . . 22 Alternative parts . . . . . . . . . . . . . . . . . . . . . . . 25 Recommended companion chip . . . . . . . . . . . 25 Support information . . . . . . . . . . . . . . . . . . . . 25 Non-linearities. . . . . . . . . . . . . . . . . . . . . . . . . 25 Integral Non-Linearity (INL). . . . . . . . . . . . . . . 25 Differential Non-Linearity (DNL).. . . . . . . . . . . 26 Dynamic parameters (single tone) . . . . . . . . . 26 Signal-to-noise and distortion (SINAD). . . . . . 26 Effective Number Of Bits (ENOB) . . . . . . . . . . 26 Total Harmonic Distortion (THD). . . . . . . . . . . 27 Signal-to-Noise ratio (S/N) . . . . . . . . . . . . . . . 27 Spurious Free Dynamic Range (SFDR) . . . . . 27 Intermodulation distortion . . . . . . . . . . . . . . . . 27 Spectral analysis (dual-tone) . . . . . . . . . . . . . 27 IMD2 (IMD3) . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Noise Power Ratio (NPR) . . . . . . . . . . . . . . . . 28 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 29 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 30 Legal information. . . . . . . . . . . . . . . . . . . . . . . 31 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 31 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Contact information. . . . . . . . . . . . . . . . . . . . . 31 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 12 August 2008 Document identifier: ADC1206S040_055_070_2

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